Regviz

Silicon Labs /MGM210P032JIA /RAC_S /SYNTHCTRL

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Interpret as SYNTHCTRL

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https://regviz.com/r/Silicon Labs/EFR32BG22C112F352GM32/RAC_NS/SYNTHCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EnablePowerbleed)MMDPOWERBALANCEDISABLE

MMDPOWERBALANCEDISABLE=EnablePowerbleed

Description

No Description

Fields

MMDPOWERBALANCEDISABLE

SYMMDPOWERBALANCEENB

0 (EnablePowerbleed): undefined

1 (DisablePowerBleed): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data